Method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge

ABSTRACT

The method of the present invention includes maintaining a first tier  101  and a second tier  102  of devices  30  that have access to a secondary bus  42  that a PCI to PCI bridge  38  services. Each device  30  that has access to secondary PCI bus  42  is categorized into either first tier  101  or a second tier  102 . The devices  30  in first tier  101  are provided more frequent opportunities to gain access to secondary PCI bus  42  than devices in low tier  102 . Next, a pending transaction is recognized when an initiating device  30  that has been categorized into second tier  102  accesses secondary PCI bus  42  and attempts a transaction that crosses PCI to PCI bridge  38  to primary PCI bus  26 . However, PCI to PCI bridge  38  is unable to complete the transaction on primary PCI bus  26 . Therefore, PCI to PCI bridge  38  is unable to provide access to any other device  30  on secondary bus  42  until the pending transaction completes. Next, device  30  that initiated the pending transaction is categorized into first tier  101  until the pending transaction is completed.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates in general to the field of PCI toPCI bridge devices and more specifically to a method and apparatus forintelligent bus arbitration in a PCI to PCI bridge.

BACKGROUND OF THE INVENTION

[0002] A peripheral component interconnect (PCI) bridge provides aconnection path between two independent PCI buses. The primary functionof a PCI to PCI bridge is to allow transactions to occur between adevice on one PCI bus and a device on the other PCI bus. System andoption card designers can use multiple PCI to PCI bridges to create anhierarchy of PCI buses. This allows system and option card designers toovercome electrical loading limits.

[0003] In a transaction between two PCI devices, the PCI device thatinitiates the transaction is called the master and the other PCI deviceis called the target. If the master and target are on different PCIbuses, the bus that the master resides on is the initiating bus. The busthat the target resides on is the target bus.

[0004] A PCI to PCI bridge has two PCI interfaces, each connected to aPCI bus. The PCI interface of the PCI to PCI bridge that is connected tothe PCI bus that is closest to the CPU is the primary interface. The PCIinterface of the PCI to PCI bridge that is connected to the PCI bus thatis farthest from the CPU is the secondary interface. Similarly, the PCIbus that is connected to the primary interface of the PCI to PCI bridgeis called the primary PCI bus. The PCI bus that is connected to thesecondary interface of the PCI to PCI bridge is called the secondarybus.

[0005] A PCI to PCI bridge acts essentially as an intermediary betweendevices located on the secondary bus and devices that are located on theprimary bus. The two interfaces of the PCI to PCI bridge bus are capableof both master and target operations. The PCI to PCI bridge acts as atarget on the initiating bus on behalf of the target that actuallyresides on the target bus. Similarly, the PCI to PCI bridge functions asa master on the target bus on behalf of the master that actually resideson the initiating bus. To devices located on the primary bus, the PCI toPCI-bridge appears as one device where it actually represents severalPCI devices that are located on the secondary bus. A detailedspecification for PCI to PCI bridges is set forth in “PCI to PCI BridgeArchitecture Specification”, Revision 1.0, Apr. 5, 1994, PCI SpecialInterest Group, Hillsboro, Oreg.

[0006] Because several PCI devices reside on the secondary bus, it ispossible that more than one of these devices will attempt to complete atransaction through the PCI to PCI bridge to a device on the primary busat the same time. Therefore, it is desirable to have some type ofarbitration scheme to decide which device on the secondary bus gets toinitiate a transaction.

[0007] One such arbitration scheme is a two tier arbitration scheme. Inthe two tier arbitration scheme, the devices located on the secondarybus are categorized into a high tier and a low tier. Each device in thehigh tier is given the opportunity to access the secondary bus. Then asingle device in the low tier is given the same opportunity. Then eachdevice in the high tier is given another opportunity to access the busbefore another device in the low tier is given an opportunity to accessthe secondary bus. This process is repeated such that devices in thehigh tier are given more opportunities to access the secondary bus thandevices in the low tier.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, a method and apparatusfor multiple tier intelligent bus arbitration on a PCI to PCI bridge isprovided that substantially eliminates or reduces problems associatedwith previously developed PCI to PCI bridge arbitration schemes.

[0009] The method of the present invention includes maintaining a firsttier and a second tier of devices that have access to the secondary busthat the PCI to PCI bridge services. Each device that has access to thesecondary PCI bus is categorized into either the first tier or thesecond tier. The devices in the first tier are provided more frequentopportunities to gain access to the secondary PCI bus than devices inthe low tier. Next, a pending transaction is recognized when aninitiating device that has been categorized into the second tieraccesses the secondary PCI bus and attempts a transaction that crossesthe PCI to PCI bridge to the primary PCI bus. However, the PCI to PCIbridge is unable to complete the transaction on the primary PCI bus.Therefore, the PCI to PCI bridge is unable to provide access to anyother device on the secondary bus until the pending transactioncompletes. Next, the device that initiated the pending transaction iscategorized into the first tier until the pending transaction iscompleted.

[0010] An apparatus of the present invention includes a PCI to PCIbridge arbiter operable to execute the two tier intelligent busarbitration scheme as described in the above method.

[0011] A further apparatus of the present invention includes a PCI toPCI bridge with an internal arbiter operable to execute the two tierintelligent bus arbitration scheme as described in the above method.

[0012] A technical advantage of the present invention is that thepending transaction will be completed faster because the initiatingdevice is placed into the first tier of high priority devices such thatit has more opportunities to access the secondary bus.

[0013] Additional technical advantages should be readily apparent fromthe drawings, description, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the present invention andadvantages thereof may be acquired by referring to the followingdescription taken in conjunction with the accompanying drawings in whichlike reference numbers indicate like features and wherein:

[0015]FIG. 1 is a block diagram of typical PCI to PCI bridgeapplications;

[0016]FIG. 2 is a functional block diagram of the typical operation of aPCI to PCI bridge;

[0017]FIG. 3 is a functional block diagram of one embodiment of a PCI toPCI bridge that contains a secondary PCI bus internal arbiter accordingto the present invention;

[0018]FIG. 4 is a diagram of one embodiment of a bridge arbitrationregister of a PCI to PCI bridge with a two tier internal arbitrationmechanism according to the present invention;

[0019]FIG. 5 is a flow chart of one embodiment of a method of a two tierintelligent bus arbitration scheme according to the present invention;

[0020]FIGS. 6A, 6B, 6C, and 6D are diagrams showing one embodiment ofthe operation of a two tier intelligent bus arbitration scheme; and

[0021]FIG. 7 is a diagram of one embodiment of the activity of a PCI toPCI bridge containing a two tier arbitration scheme with and without anintelligent bus arbitration scheme according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022]FIG. 1 is a block diagram of typical PCI to PCI bridgeapplications. A CPU 10 connects to memory 18 via host bus 14. A hostbridge 22 connects host bus 14 to a PCI bus 26. PCI bus 26 connects PCIdevices 30 to host bridge 22. PCI bus 26 also connects to a PCI to PCIbridge 38. PCI to PCI bridge 38 in turn connects to PCI option cards 44via PCI bus 42. A second PCI to PCI bridge 39 operates via PCI bus 48 toconnect PCI devices 32 to PCI bus 42.

[0023] The bus that connects to a PCI to PCI bridge and is closest tothe CPU is the primary bus and connects to the primary interface of thePCI to PCI bridge. Therefore, for PCI to PCI bridge 38, interface 36 isthe primary interface and PCI bus 26 is the primary bus.

[0024] Accordingly, interface 40 is the secondary interface and PCI bus42 is the secondary bus. For PCI to PCI bridge 39, interface 37 is theprimary interface and PCI bus 42 is the primary bus, while interface 41is the secondary interface and PCI bus 48 is the secondary bus.

[0025] In a configuration such as that shown in FIG. 1, each PCI to PCIbridge and each PCI bus are numbered for identification. The PCI busthat is the secondary bus for the host bridge is given the name “PCI BUS0.” Therefore, PCI bus 26 is PCI BUS 0. The PCI to PCI bridge that usesPCI BUS 0 as its primary interface is given the name “PCI-PCI BRIDGE 1.”This corresponds to PCI to PCI bridge 38. The PCI bus that acts as thesecondary bus to a PCI to PCI bridge is given the number of that PCI toPCI bridge. Therefore, PCI bus 42 is called “PCI BUS 1” because it isthe secondary bus to PCI-PCI BRIDGE 1 (PCI to PCI bridge 38). Each PCIto PCI bridge and each PCI bus is named in this fashion. Thus, for FIG.1, PCI to PCI bridge 39 is named “PCI-PCI BRIDGE 2” and PCI bus 48 is“PCI BUS 2.”

[0026] Electrical loading limits, as specified in the PCI Local BusSpecification, Revision 2.1, allow only ten PCI device loads per PCIbus. Therefore, a system that requires more than ten PCI device loadsrequires a PCI to PCI bridge. For example, in FIG. 1, a maximum of 10PCI devices 30 may connect to PCI bus 26 and host bridge 22. However,PCI to PCI bridge 38 appears as one device to PCI bus 26 and host bridge22. This allows option cards 44 that contain further PCI devices 32 toaccess PCI bus 26 and host bridge 22 maintaining the specifiedelectrical loading limits.

[0027] In operation, if PCI device 32 initiates a transaction to memory18, PCI device 32 is the master and memory 18 is the target. To completethe transaction, PCI device 32 acts as a master along PCI bus 48 tosecondary interface 41 of PCI to PCI bridge 39. Then, primary interface37 of PCI to PCI bridge 39 acts as a master to complete a transaction tosecondary interface 40 of PCI to PCI bridge 38. Next, primary interface36 of PCI to PCI bridge 38 initiates a transaction as master tosecondary interface of host bridge 22. Host bridge 22 then acts asmaster for a transaction to memory 18.

[0028]FIG. 2 is a functional block diagram of the typical operation of aPCI to PCI bridge indicated generally at 38. Data moving downstreamfirst encounters a primary interface 36. This action initiates a primarytarget interface 60. PCI to PCI bridge 38 is acting as the target of thetransaction that is taking place on the primary bus. Next, a secondarymaster interface 64 is triggered, in order for PCI to PCI bridge 38 toact as the master of the transaction on the secondary bus. When atransaction moves upstream, a secondary target interface 68 isinitiated. PCI to PCI bridge 38 is acting as the target of thistransaction that is taking place on the secondary bus. Then a primarymaster interface 72 is initiated. Here, PCI to PCI bridge 38 acts as themaster to the transaction on the primary bus. These transactions areaffected by configuration registers 76 that determine thecharacteristics of PCI to PCI bridge 38. Furthermore, optional databuffers 80 may exist on PCI to PCI bridge 38 to buffer data involved intransactions across PCI to PCI bridge 38.

[0029]FIG. 3 is a functional block diagram of one embodiment of a PCI toPCI bridge that contains a secondary PCI bus internal arbiter accordingto the present invention. PCI to PCI bridge, indicated generally at 38,contains a primary interface 36 and a secondary interface 40. Primarypinouts 43 comprise the signals that interact with the primary bus onprimary interface 36. Secondary pinouts 45 contain the signals thatinterface with the secondary bus and secondary interface 40. Secondaryinterface 40 also contains pinouts 45 that interact with a secondary PCIbus internal arbiter 100. PCI to PCI bridge 38 of this embodiment alsocontains configuration registers 76 and data buffers 80. In operation,PCI to PCI bridge 38 interprets the signals on primary pinouts 43 andsecondary pinouts 45 in order to transmit transactions upstream anddownstream.

[0030] If more than one device on the secondary bus desires to accesssecondary interface 40, secondary PCI bus internal arbiter 100determines which device may use PCI to PCI bridge 38. In one embodiment,internal arbiter 100 implements a two tier arbitration scheme, with ahigh tier and a low tier, as described below.

[0031]FIG. 4 is a diagram of one embodiment of a bridge arbitrationregister of a PCI to PCI bridge with a two tier internal arbitrationmechanism according to the present invention. The embodimentcontemplates a system whereby the PCI to PCI bridge may service up tosix PCI devices that are on the secondary bus. Including the PCI to PCIbridge, there are seven devices that may access the secondary bus. Bits0-6 allow the user to categorize each device in one of the two tiers. AsFIG. 4 shows, the default for this embodiment places the PCI to PCIbridge in the higher priority tier while all other devices are in thelower priority tier.

[0032] Such a two tier arbitration scheme presents a problem when adevice in the low tier initiates but does not complete a transactionacross the PCI to PCI bridge. That is, a master device accessed thesecondary bus and indicated to the PCI to PCI bridge that the PCI to PCIbridge needs to access the primary bus and initiate a transaction with adevice located on the primary bus. However, the PCI to PCI bridge wasunable to complete the transaction on the primary bus. Where the PCI toPCI bridge can only handle one transaction at a time on the primary bus,the incomplete transaction is pending. Therefore, the PCI to PCI bridgeinforms the master device to retry the attempted transaction.Furthermore, since the PCI to PCI bridge has not completed the firsttransaction, it must tell any other device that attempts a transactionto also retry. However, in a simple two tier arbitration scheme, theinitial master device, if it is in the low tier, must wait until all thehigh priority devices have had an opportunity to access the bus and theneach low priority device in sequence has an opportunity to access thesecondary bus. Even when the PCI to PCI bridge completes the transactionon the primary bus, it must wait until the master device again has anopportunity to access the secondary bus to complete the transaction.Because the master device is in the low tier, this can result insignificant non-utilization of the PCI to PCI bridge.

[0033]FIG. 5 is a flow chart of one embodiment of a method of a two tierintelligent bus arbitration scheme according to the present invention.This methodology resides inside internal arbiter 100. In step 120, ahigh and low tier of devices with access to a secondary PCI bus ismaintained. Next, at step 124, each device with access to the secondarybus is categorized into either the high tier or the low tier. Then atstep 126, access to the secondary bus is provided such that the devicesin the high tier have more opportunities than devices in the low tier toaccess the secondary bus. Next at step 128, it is determined that if adevice in the low tier attempts but cannot complete a transaction overthe PCI to PCI bridge, the device is placed into the high tier. At step130, after the transaction completes, the device is placed back into thelow tier. In operation, this method determines that when a device in thelow tier must have access to the secondary bus such that it can completea transaction that is pending on the primary bus, that device is placedinto the high tier in order to allow the transaction to complete morequickly.

[0034]FIGS. 6A, 6B, 6C, and 6D are diagrams showing one embodiment ofthe operation of a two tier intelligent bus arbitration scheme. FIG. 6Ashows a typical placement of a PCI to PCI bridge. Memory 18 resides onPCI primary bus 26 which connects to primary interface 36 of PCI to PCIbridge 38. PCI to PCI bridge 38 contains secondary PCI bus internalarbiter 100. PCI to PCI bridge 38 has a secondary interface 40 whichconnects to PCI secondary bus 42. PCI devices 30 reside on PCI secondarybus 42. PCI devices 30 are labeled 0, 1, 2, 3, 4, and 5. In operation,when PCI device 0 desires to access memory 18, it can conduct atransaction through PCI to PCI bridge 38. It can do so by firstinitiating a transaction over PCI secondary bus 42 to secondaryinterface 40. In this portion of the transaction, PCI to PCI bridge 38is acting as the target and PCI device 0 is acting as the master. PCI toPCI bridge 38 must in turn act as the master to initiate a transactionover primary interface 36 to primary PCI bus 26 in order to gain accessto memory 18. In this embodiment, PCI to PCI bridge 38 only conducts onesuch transaction at a time. If PCI to PCI bridge 38 is conducting thistransaction for PCI device 0, then it is unable to transact a similartransaction for any other PCI device. In such a state, PCI to PCI bridge38 contains a pending transaction. If the transaction is still pendingat the end of PCI device 0's opportunity to access PCI secondary bus 42,the transaction will remain pending until PCI device 0 has anotheropportunity to access PCI secondary bus 42. While this transaction ispending, PCI to PCI bridge 38 of the present invention initiates a twotier intelligent bus arbitration scheme in order to expedite thetransaction.

[0035]FIG. 6B is a diagram of an operation of a two tier arbitrationscheme as implemented by secondary PCI bus internal arbiter 100. Thereis a high tier 101 and a low tier 102. Each PCI device 0-5 iscategorized either into high tier 101 or low tier 102. Each device 0-5has an opportunity to access secondary PCI bus 42 in the followingmanner. First, each device in high tier 101 has an opportunity to accesssecondary PCI bus 42. Then, one of the devices in low tier 102 has anopportunity to access secondary PCI bus 42. Therefore, if PCI devices0-5 are categorized as in FIG. 6B, then devices 0-5 have opportunitiesto access secondary PCI bus 42 in the following order: 0, 1, 2, 3, 0, 1,2, 4, 0, 1, 2, 5.

[0036]FIG. 6C is a diagram of further operation of a two tierarbitration scheme. FIG. 6C shows a situation whereby PCI devices 0-5are all initially categorized in low tier 102. Therefore, devices 0-5have opportunities to access secondary PCI bus 42 in the followingorder: 0, 1, 2, 3, 4, 5.

[0037]FIG. 6D is a diagram of the operation of an embodiment of anintelligent two tier bus arbitration scheme, according to the presentinvention. In FIG. 6D, internal arbiter 100 has determined that PCIdevice 0 has initiated a transaction that is still pending. Therefore,PCI device 0 is moved temporarily into high tier 101. While PCI device 0is in high tier 101, the opportunity for each device to access secondaryPCI bus 42 will follow the order: 0, 1, 0, 2, 0, 3, 0, 4, 0, 5. FIGS. 6Cand 6D show that the present embodiment provides more of an opportunityto access secondary PCI bus 42 when secondary PCI bus internal arbiterdetermines that a low tier device has a pending transaction. Therefore,the pending transaction can be completed more quickly.

[0038]FIG. 7 is a diagram of one embodiment of the activity of a PCI toPCI bridge containing a two tier arbitration scheme with and without anintelligent bus arbitration scheme according to the present invention.The top portion of FIG. 7 shows each device 0-5 is in the low tier andthus each device has an equal opportunity to access the secondary bus.This example contemplates that a task initiated by device 0 begins attime A and completes at time C. However, if all devices remain in thelow tier, device 0 will not get another opportunity to access thesecondary bus until time G. Therefore, the PCI to PCI bridge cannotcomplete the transaction and cannot process another transaction untiltime H. The bottom portion of FIG. 7 shows the implementation of a twotier intelligent bus arbitration scheme according to the presentinvention. Once again, a task initiated by device 0 begins at time A andcompletes at time C. However, the arbiter has placed 0 in the high tier,thus device 0 has an opportunity to access the secondary bus morefrequently. Therefore, the transaction is completed at time C and thebridge is free to process another transaction at time D.

[0039] Although the present invention has been described in detail, itshould be understood that various changes, substitutions and alterationscan be made hereto without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A method for a multiple tier intelligent busarbitration scheme for a PCI to PCI bridge, comprising the steps of:maintaining a first tier and a second tier of devices that have accessto a secondary PCI bus; categorizing each device that has access to thesecondary PCI bus into the first tier or the second tier; providingdevices in the first tier more frequent opportunities to gain access tothe secondary PCI bus than devices in the second tier; recognizing apending transaction when an initiating device in the second tieraccesses the secondary PCI bus and attempts a transaction that crossesthe PCI to PCI bridge to a primary PCI bus, but the PCI to PCI bridge isunable to complete the transaction on the primary PCI bus, such that thePCI to PCI bridge is unable to provide access to the primary PCI bus toother devices on the secondary bus; and categorizing the initiatingdevice into the first tier until the pending transaction is completed.2. The method of claim 1 , whereby the step of providing devices in thehigh tier more of an opportunity to gain access to the secondary PCI busthan devices in the low tier is comprised of the steps of: maintaining asequential order of the devices categorized in the second tier;providing an opportunity for each device in the first tier anopportunity to gain access to the secondary PCI bus; providing anopportunity for a single device in the second tier an opportunity togain access to the secondary bus; repeating the above steps to granteach device an opportunity to gain access to the secondary bus, suchthat the device in the second tier that is granted an opportunity toaccess the secondary bus is the next device in the sequential order fromthe previous device in the second tier that was allowed an opportunityto access the secondary bus.
 3. The method of claim 1 further comprisingthe step of categorizing the PCI to PCI bridge into the first or secondtier as a device with access to the secondary PCI bus.
 4. The method ofclaim 3 further comprising the step of initially placing the PCI to PCIbridge into the first tier.
 5. The method of claim 1 whereby the step ofcategorizing each device with access to the secondary bus comprisescategorizing six PCI devices and the PCI to PCI bridge.
 6. The method ofclaim 5 further comprising the step of initially placing the PCI to PCIbridge into the first tier and all other devices into the second tier.7. A PCI to PCI bridge arbiter with a multiple tier intelligent busarbitration scheme, comprising: an arbiter associated with a PCI to PCIbridge operable to: receive from the PCI to PCI bridge information ondevices associated with a secondary bus; maintain a first tier and asecond tier of devices that have access to the secondary PCI bus;categorize each device that has access to the secondary PCI bus into thefirst tier or the second tier; provide data to the PCI to PCI bridgesuch that the PCI to PCI bridge provides devices in the first tier morefrequent opportunities to gain access to the secondary PCI bus thandevices in the second tier; recognize a pending transaction when aninitiating device in the second tier accesses the secondary PCI bus andattempts a transaction that crosses the PCI to PCI bridge to primary PCIbus, but the PCI to PCI bridge is unable to complete the transaction onthe primary PCI bus, such that the PCI to PCI bridge is unable toprovide access to the primary PCI bus to other devices on the secondarybus; and categorize the initiating device into the first tier until thepending transaction is completed.
 8. The PCI to PCI bridge arbiter ofclaim 7 , whereby the arbiter is further operable to: maintain asequential order of the devices categorized in the second tier; providedata to the PCI to PCI bridge such that the PCI to PCI bridge providesan opportunity for each device in the first tier an opportunity to gainaccess to the secondary PCI bus; provide data to the PCI to PCI bridgesuch that the PCI to PCI bridge provides an opportunity for a singledevice in the second tier an opportunity to gain access to the secondarybus; repeat the above steps such that the PCI to PCI bridge grants eachdevice an opportunity to gain access to the secondary bus, such that thedevice in the second tier that is granted an opportunity to access thesecondary bus is the next device in the sequential order from theprevious device in the second tier that was allowed an opportunity toaccess the secondary bus.
 9. The PCI to PCI bridge arbiter of claim 7whereby the arbiter is further operable to categorize the PCI to PCIbridge into the first or second tier as a device with access to thesecondary PCI bus.
 10. The PCI to PCI bridge arbiter of claim 9 wherebythe arbiter is further operable to initially place the PCI to PCI bridgeinto the first tier.
 11. The PCI to PCI bridge arbiter of claim 7whereby the arbiter is further operable to categorize six PCI devicesand the PCI to PCI bridge into the first tier or second tier.
 12. ThePCI to PCI bridge arbiter of claim 11 whereby the arbiter is furtheroperable to initially place the PCI to PCI bridge into the first tierand all other devices into the second tier.
 13. A PCI to PCI bridge witha multiple tier intelligent bus arbitration scheme, comprising: aprimary bus interface operable to communicate with PCI devicesassociated with a primary bus; a secondary bus interface associated withthe primary bus interface and operable to communicate with PCI devicesassociated with a secondary bus; a secondary PCI bus internal arbiterassociated with the secondary bus interface operable to: maintain afirst tier and a second tier of devices that have access to thesecondary PCI bus; categorize each device that has access to thesecondary PCI bus into the first tier or the second tier; providedevices in the first tier more frequent opportunities to gain access tothe secondary PCI bus than devices in the second tier; recognize apending transaction when an initiating device in the second tieraccesses the secondary PCI bus and attempts a transaction that crossesthe PCI to PCI bridge to the primary PCI bus, but the PCI to PCI bridgeis unable to complete the transaction on the primary PCI bus, such thatthe PCI to PCI bridge is unable to provide access to the primary PCI busto other devices on the secondary bus; and categorize the initiatingdevice into the first tier until the pending transaction is completed.14. The PCI to PCI bridge of claim 13 , whereby the secondary PCI businternal arbiter is further operable to: maintain a sequential order ofthe devices categorized in the second tier; provide an opportunity foreach device in the first tier an opportunity to gain access to thesecondary PCI bus; provide an opportunity for a single device in thesecond tier an opportunity to gain access to the secondary bus; repeatthe above steps to grant each device an opportunity to gain access tothe secondary bus, such that the device in the second tier that isgranted an opportunity to access the secondary bus is the next device inthe sequential order from the previous device in the second tier thatwas allowed an opportunity to access the secondary bus.
 15. The PCI toPCI bridge of claim 13 whereby the secondary PCI bus internal arbiter isfurther operable to categorize the PCI to PCI bridge into the first orsecond tier as a device with access to the secondary PCI bus.
 16. ThePCI to PCI bridge of claim 15 whereby the secondary PCI bus internalarbiter is further operable to initially place the PCI to PCI bridgeinto the first tier.
 17. The PCI to PCI bridge of claim 13 whereby thesecondary PCI bus internal arbiter is further operable to categorize sixPCI devices and the PCI to PCI bridge into the first tier or secondtier.
 18. The PCI to PCI bridge of claim 17 whereby the secondary PCIbus internal arbiter is further operable to initially place the PCI toPCI bridge into the first tier and all other devices into the secondtier.
 19. The PCI to PCI bridge of claim 13 wherein the first tier is ahigh tier and the second tier is a low tier.